diff options
| author | Palmer Dabbelt <palmer@rivosinc.com> | 2024-02-07 13:22:54 +0100 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-03-08 19:47:48 +1000 |
| commit | 09c4e887595a5df9d80006a3632d43249b986c54 (patch) | |
| tree | 7c7fd9e27bf688ced5c38f1319406359ac048ebe /target/riscv/translate.c | |
| parent | 4c1608caa4d567de5e73265ac79fdfd517a4189a (diff) | |
RISC-V: Add support for Ztso
The Ztso extension is already ratified, this adds it as a CPU property
and adds various fences throughout the port in order to allow TSO
targets to function on weaker hosts. We need no fences for AMOs as
they're already SC, the places we need barriers are described.
These fences are placed in the RISC-V backend rather than TCG as is
planned for x86-on-arm64 because RISC-V allows heterogeneous (and
likely soon dynamic) hart memory models.
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-ID: <20240207122256.902627-2-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/translate.c')
| -rw-r--r-- | target/riscv/translate.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 177418b2b9..ea5d52b2ef 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -109,6 +109,8 @@ typedef struct DisasContext { /* PointerMasking extension */ bool pm_mask_enabled; bool pm_base_enabled; + /* Ztso */ + bool ztso; /* Use icount trigger for native debug */ bool itrigger; /* FRM is known to contain a valid value. */ @@ -1196,6 +1198,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->cs = cs; ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED); ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); + ctx->ztso = cpu->cfg.ext_ztso; ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); ctx->zero = tcg_constant_tl(0); ctx->virt_inst_excp = false; |