diff options
| author | Alistair Francis <alistair.francis@wdc.com> | 2020-04-03 14:05:01 -0700 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-06-19 08:24:07 -0700 |
| commit | b8429ded723ec52568e05f6a24ed78c93224687c (patch) | |
| tree | cbb8c8aed41e4ea73000e8e04123059855697586 /target/riscv/translate.c | |
| parent | 88914473e748db20d8e18b9735f647a683319fa6 (diff) | |
target/riscv: Move the hfence instructions to the rvh decode
Also correct the name of the VVMA instruction.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/riscv/translate.c')
| -rw-r--r-- | target/riscv/translate.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 43bf7e39a6..ce71ca7a92 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -711,6 +711,7 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, #include "insn_trans/trans_rva.inc.c" #include "insn_trans/trans_rvf.inc.c" #include "insn_trans/trans_rvd.inc.c" +#include "insn_trans/trans_rvh.inc.c" #include "insn_trans/trans_privileged.inc.c" /* Include the auto-generated decoder for 16 bit insn */ |