diff options
| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-03-07 16:13:58 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-05-05 10:49:50 +1000 |
| commit | e0a3054f18e20602768d328b0cb7d5910253a327 (patch) | |
| tree | e7970e260b57f9f0e3141a9c81e3768dd88b3c82 /target/riscv/translate.c | |
| parent | c4935b58422d4692bae6f37069a5cbb748656b29 (diff) | |
target/riscv: add support for Zcb extension
Add encode and trans* functions support for Zcb instructions.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230307081403.61950-6-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/translate.c')
| -rw-r--r-- | target/riscv/translate.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/riscv/translate.c b/target/riscv/translate.c index d1fdd0c2d7..3634137d85 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1091,6 +1091,8 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) /* Include the auto-generated decoder for 16 bit insn */ #include "decode-insn16.c.inc" +#include "insn_trans/trans_rvzce.c.inc" + /* Include decoders for factored-out extensions */ #include "decode-XVentanaCondOps.c.inc" |