diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2022-08-11 13:48:03 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2022-09-06 08:04:26 +0100 |
| commit | 306c872103b4d0986c9f671eb7538b0b70bf69b5 (patch) | |
| tree | 17360b109ccbc2357188396e082ed033cd13ef9e /target/riscv/translate.c | |
| parent | dac8d19bdb3ccaafbcbd2df34135464964232a8f (diff) | |
accel/tcg: Add pc and host_pc params to gen_intermediate_code
Pass these along to translator_loop -- pc may be used instead
of tb->pc, and host_pc is currently unused. Adjust all targets
at one time.
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Acked-by: Ilya Leoshkevich <iii@linux.ibm.com>
Tested-by: Ilya Leoshkevich <iii@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/riscv/translate.c')
| -rw-r--r-- | target/riscv/translate.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 63b04e8a94..38666ddc91 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1196,11 +1196,12 @@ static const TranslatorOps riscv_tr_ops = { .disas_log = riscv_tr_disas_log, }; -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns, + target_ulong pc, void *host_pc) { DisasContext ctx; - translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns); + translator_loop(cs, tb, max_insns, pc, host_pc, &riscv_tr_ops, &ctx.base); } void riscv_translate_init(void) |