diff options
| author | Alistair Francis <alistair.francis@wdc.com> | 2020-01-31 17:03:08 -0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmerdabbelt@google.com> | 2020-02-27 13:46:33 -0800 |
| commit | e44b50b5b2e508fdd24915ab0e44ac49685e1de3 (patch) | |
| tree | e0a6d6fa3b43bbab5534860e590114d95e90f0b6 /target/riscv/translate.c | |
| parent | 551fa7e8a695ea5fd1cca8ffd318556855bbf54f (diff) | |
target/riscv: Add the MSTATUS_MPV_ISSET helper macro
Add a helper macro MSTATUS_MPV_ISSET() which will determine if the
MSTATUS_MPV bit is set for both 32-bit and 64-bit RISC-V.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'target/riscv/translate.c')
| -rw-r--r-- | target/riscv/translate.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv/translate.c b/target/riscv/translate.c index b51ab92068..43bf7e39a6 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -755,7 +755,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->virt_enabled = riscv_cpu_virt_enabled(env); if (env->priv_ver == PRV_M && get_field(env->mstatus, MSTATUS_MPRV) && - get_field(env->mstatus, MSTATUS_MPV)) { + MSTATUS_MPV_ISSET(env)) { ctx->virt_enabled = true; } else if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env) && |