diff options
| author | Alistair Francis <alistair.francis@wdc.com> | 2021-12-20 16:49:16 +1000 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-01-08 15:46:10 +1000 |
| commit | 48eaeb56debf91817dea00a2cd9c1f6c986eb531 (patch) | |
| tree | 59d55faafca9293f474bbfae6e42b1686bd16180 /target/riscv/translate.c | |
| parent | 86d0c457396b1a789fe2740f7bd8d476ea426298 (diff) | |
target/riscv: Implement the stval/mtval illegal instruction
The stval and mtval registers can optionally contain the faulting
instruction on an illegal instruction exception. This patch adds support
for setting the stval and mtval registers.
The RISC-V spec states that "The stval register can optionally also be
used to return the faulting instruction bits on an illegal instruction
exception...". In this case we are always writing the value on an
illegal instruction.
This doesn't match all CPUs (some CPUs won't write the data), but in
QEMU let's just populate the value on illegal instructions. This won't
break any guest software, but will provide more information to guests.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20211220064916.107241-4-alistair.francis@opensource.wdc.com
Diffstat (limited to 'target/riscv/translate.c')
| -rw-r--r-- | target/riscv/translate.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 9e4f9c3342..615048ec87 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -208,6 +208,9 @@ static void generate_exception_mtval(DisasContext *ctx, int excp) static void gen_exception_illegal(DisasContext *ctx) { + tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env, + offsetof(CPURISCVState, bins)); + generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); } |