diff options
author | Richard Henderson <richard.henderson@linaro.org> | 2021-10-19 20:17:04 -0700 |
---|---|---|
committer | Alistair Francis <alistair.francis@wdc.com> | 2021-10-22 23:35:43 +1000 |
commit | 80347ae9f26dfafbd358d7d8d9ad175a2a624365 (patch) | |
tree | 229b5315cff919375e665d94018e92ace24c3329 /target/riscv/translate.c | |
parent | 7667cafd5a0d173d1853b4d8414d4a98df1374dc (diff) |
target/riscv: Use gen_arith_per_ol for RVM
The multiply high-part instructions require a separate
implementation for RV32 when TARGET_LONG_BITS == 64.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-11-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/translate.c')
-rw-r--r-- | target/riscv/translate.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/target/riscv/translate.c b/target/riscv/translate.c index afd59ef690..cb515e2a3c 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -403,6 +403,22 @@ static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, return true; } +static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, + void (*f_tl)(TCGv, TCGv, TCGv), + void (*f_32)(TCGv, TCGv, TCGv)) +{ + int olen = get_olen(ctx); + + if (olen != TARGET_LONG_BITS) { + if (olen == 32) { + f_tl = f_32; + } else { + g_assert_not_reached(); + } + } + return gen_arith(ctx, a, ext, f_tl); +} + static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, void (*func)(TCGv, TCGv, target_long)) { |