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authorBastian Koppelmann <kbastian@mail.uni-paderborn.de>2019-02-13 07:54:00 -0800
committerBastian Koppelmann <kbastian@mail.uni-paderborn.de>2019-03-13 10:40:50 +0100
commit090cc2c898a04e42350eabf1bcf7d245471603f9 (patch)
treec1a40ddd73e66c4fa8b9362738e9300933bdbbab /target/riscv/translate.c
parent9e92c57d834cd50ab088d75510c3c720878eef13 (diff)
target/riscv: Remove manual decoding from gen_branch()
We now utilizes argument-sets of decodetree such that no manual decoding is necessary. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
Diffstat (limited to 'target/riscv/translate.c')
-rw-r--r--target/riscv/translate.c47
1 files changed, 0 insertions, 47 deletions
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 9dee2ec242..a3d5cdbad8 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -531,53 +531,6 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
ctx->base.is_jmp = DISAS_NORETURN;
}
-static void gen_branch(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
- target_long bimm)
-{
- TCGLabel *l = gen_new_label();
- TCGv source1, source2;
- source1 = tcg_temp_new();
- source2 = tcg_temp_new();
- gen_get_gpr(source1, rs1);
- gen_get_gpr(source2, rs2);
-
- switch (opc) {
- case OPC_RISC_BEQ:
- tcg_gen_brcond_tl(TCG_COND_EQ, source1, source2, l);
- break;
- case OPC_RISC_BNE:
- tcg_gen_brcond_tl(TCG_COND_NE, source1, source2, l);
- break;
- case OPC_RISC_BLT:
- tcg_gen_brcond_tl(TCG_COND_LT, source1, source2, l);
- break;
- case OPC_RISC_BGE:
- tcg_gen_brcond_tl(TCG_COND_GE, source1, source2, l);
- break;
- case OPC_RISC_BLTU:
- tcg_gen_brcond_tl(TCG_COND_LTU, source1, source2, l);
- break;
- case OPC_RISC_BGEU:
- tcg_gen_brcond_tl(TCG_COND_GEU, source1, source2, l);
- break;
- default:
- gen_exception_illegal(ctx);
- return;
- }
- tcg_temp_free(source1);
- tcg_temp_free(source2);
-
- gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
- gen_set_label(l); /* branch taken */
- if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + bimm) & 0x3)) {
- /* misaligned */
- gen_exception_inst_addr_mis(ctx);
- } else {
- gen_goto_tb(ctx, 0, ctx->base.pc_next + bimm);
- }
- ctx->base.is_jmp = DISAS_NORETURN;
-}
-
static void gen_load(DisasContext *ctx, uint32_t opc, int rd, int rs1,
target_long imm)
{