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authorFrank Chang <frank.chang@sifive.com>2021-12-10 15:56:49 +0800
committerAlistair Francis <alistair.francis@wdc.com>2021-12-20 14:53:31 +1000
commit75804f71319706308dd48441b408abc09481c5ae (patch)
treef0aed16dadb8f6d4aae8476da6cf8d97a91f82d5 /target/riscv/translate.c
parent3ce4c09df75529da0a5798279a01e24c02df15da (diff)
target/riscv: add "set round to odd" rounding mode helper function
helper_set_rounding_mode() is responsible for SIGILL, and "round to odd" should be an interface private to translation, so add a new independent helper_set_rod_rounding_mode(). Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-64-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/translate.c')
-rw-r--r--target/riscv/translate.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 3688e80d03..b4df21bda3 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -30,6 +30,7 @@
#include "exec/log.h"
#include "instmap.h"
+#include "internals.h"
/* global register indices */
static TCGv cpu_gpr[32], cpu_pc, cpu_vl;
@@ -403,6 +404,12 @@ static void gen_set_rm(DisasContext *ctx, int rm)
return;
}
ctx->frm = rm;
+
+ if (rm == RISCV_FRM_ROD) {
+ gen_helper_set_rod_rounding_mode(cpu_env);
+ return;
+ }
+
gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm));
}