diff options
| author | Michael Clark <mjc@sifive.com> | 2019-03-16 01:21:12 +0000 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-03-19 05:14:40 -0700 |
| commit | 929f0a7fc40d7123ddda4c9dbd78a1806999b4f7 (patch) | |
| tree | 3befad4f4f5aebdc43c661520c5b330b67bc9533 /target/riscv/trace-events | |
| parent | acbbb94e5730c9808830938e869d243014e2923a (diff) | |
RISC-V: Convert trap debugging to trace events
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'target/riscv/trace-events')
| -rw-r--r-- | target/riscv/trace-events | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/riscv/trace-events b/target/riscv/trace-events new file mode 100644 index 0000000000..48af0373df --- /dev/null +++ b/target/riscv/trace-events @@ -0,0 +1,2 @@ +# target/riscv/cpu_helper.c +riscv_trap(uint64_t hartid, bool async, uint64_t cause, uint64_t epc, uint64_t tval, const char *desc) "hart:%"PRId64", async:%d, cause:%"PRId64", epc:0x%"PRIx64", tval:0x%"PRIx64", desc=%s" |