aboutsummaryrefslogtreecommitdiff
path: root/target/riscv/pmp.c
diff options
context:
space:
mode:
authorAkihiko Odaki <akihiko.odaki@daynix.com>2023-08-18 12:40:58 +0900
committerAlistair Francis <alistair.francis@wdc.com>2023-09-11 11:45:55 +1000
commita7c272df82af11c568ea83921b04334791dccd5e (patch)
tree33aaa7a13d6422e7e193ac5de1f75b3889d34b0b /target/riscv/pmp.c
parent7d496bb50233d861032fb22b4fae050b246c9197 (diff)
target/riscv: Allocate itrigger timers only once
riscv_trigger_init() had been called on reset events that can happen several times for a CPU and it allocated timers for itrigger. If old timers were present, they were simply overwritten by the new timers, resulting in a memory leak. Divide riscv_trigger_init() into two functions, namely riscv_trigger_realize() and riscv_trigger_reset() and call them in appropriate timing. The timer allocation will happen only once for a CPU in riscv_trigger_realize(). Fixes: 5a4ae64cac ("target/riscv: Add itrigger support when icount is enabled") Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20230818034059.9146-1-akihiko.odaki@daynix.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/pmp.c')
0 files changed, 0 insertions, 0 deletions