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| author | Peter Maydell <peter.maydell@linaro.org> | 2019-04-29 17:35:59 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-04-29 17:35:59 +0100 |
| commit | 8859ba3c9625e7ceb5599f457a344bcd7c5e112b (patch) | |
| tree | 0894e5074370823728247fdffb2f4257b961becf /target/riscv/op_helper.c | |
| parent | d87513c0abcbcd856f8e1dee2f2d18903b2c3ea2 (diff) | |
target/arm: Decode FP instructions for M profile
Correct the decode of the M-profile "coprocessor and
floating-point instructions" space:
* op0 == 0b11 is always unallocated
* if the CPU has an FPU then all insns with op1 == 0b101
are floating point and go to disas_vfp_insn()
For the moment we leave VLLDM and VLSTM as NOPs; in
a later commit we will fill in the proper implementation
for the case where an FPU is present.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190416125744.27770-7-peter.maydell@linaro.org
Diffstat (limited to 'target/riscv/op_helper.c')
0 files changed, 0 insertions, 0 deletions