diff options
| author | Michael Clark <mjc@sifive.com> | 2018-03-06 10:51:53 +1300 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2018-10-17 13:02:19 -0700 |
| commit | 426f03482c8d2b98613f92a76bd034ac6bb0bc7a (patch) | |
| tree | 9b895f90a191e0abd95795dcc26cd0578f41fb2d /target/riscv/op_helper.c | |
| parent | df354dd41064491342c2f1b5d4743eed40f0fa27 (diff) | |
RISC-V: Update CSR and interrupt definitions
* Add user-mode CSR defininitions.
* Reorder CSR definitions to match the specification.
* Change H mode interrupt comment to 'reserved'.
* Remove unused X_COP interrupt.
* Add user-mode interrupts.
* Remove erroneous until comments on machine mode interrupts.
* Move together paging mode and page table bit definitions.
* Move together interrupt and exception cause definitions.
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'target/riscv/op_helper.c')
| -rw-r--r-- | target/riscv/op_helper.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 495390ab1c..3726299d4a 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -90,7 +90,7 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write, target_ulong csrno) { #ifndef CONFIG_USER_ONLY - uint64_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_X_COP); + uint64_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP; uint64_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP; #endif |