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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-08-17 16:37:56 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair@alistair23.me> | 2022-09-27 07:04:38 +1000 |
| commit | a412829406905a7edf7a33ded754f89f50a33af1 (patch) | |
| tree | 32d69a59506230c032da7848791ec0cee50cac5b /target/riscv/op_helper.c | |
| parent | 513eb437aef7687ad1963d935ffb884fff3c4775 (diff) | |
target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h}
- modify check for mcounteren to work in all less-privilege mode
- modify check for scounteren to work only when S mode is enabled
- distinguish the exception type raised by check for scounteren between U
and VU mode
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220817083756.12471-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/op_helper.c')
0 files changed, 0 insertions, 0 deletions