diff options
| author | Yifei Jiang <jiangyifei@huawei.com> | 2020-10-26 19:55:26 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-11-03 07:17:23 -0800 |
| commit | f7697f0e629eb75d411bc6f314c6fff68fa4c238 (patch) | |
| tree | 51da5a47ea36ea88aa2b44799b6ab2eab912a0a0 /target/riscv/meson.build | |
| parent | 284d697c74ef3f4210cbccc5cd6b4894740e4ab3 (diff) | |
target/riscv: Add basic vmstate description of CPU
Add basic CPU state description to the newly created machine.c
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201026115530.304-3-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/meson.build')
| -rw-r--r-- | target/riscv/meson.build | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/target/riscv/meson.build b/target/riscv/meson.build index abd647fea1..14a5c62dac 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -27,7 +27,8 @@ riscv_ss.add(files( riscv_softmmu_ss = ss.source_set() riscv_softmmu_ss.add(files( 'pmp.c', - 'monitor.c' + 'monitor.c', + 'machine.c' )) target_arch += {'riscv': riscv_ss} |