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authorAtish Patra <atishp@rivosinc.com>2022-08-24 15:13:57 -0700
committerAlistair Francis <alistair.francis@wdc.com>2022-09-07 09:19:15 +0200
commit3ec0fe18a31fabfe999b480e4c21847ac0d51560 (patch)
tree944238c6356ff239d1a06129b81121b0ecaa5590 /target/riscv/machine.c
parent43888c2f1823212b1064a6a94d65d8acaf954478 (diff)
target/riscv: Add vstimecmp support
vstimecmp CSR allows the guest OS or to program the next guest timer interrupt directly. Thus, hypervisor no longer need to inject the timer interrupt to the guest if vstimecmp is used. This was ratified as a part of the Sstc extension. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220824221357.41070-4-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/machine.c')
-rw-r--r--target/riscv/machine.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 622fface48..4ba55705d1 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -92,6 +92,7 @@ static const VMStateDescription vmstate_hyper = {
VMSTATE_UINTTL(env.hgeie, RISCVCPU),
VMSTATE_UINTTL(env.hgeip, RISCVCPU),
VMSTATE_UINT64(env.htimedelta, RISCVCPU),
+ VMSTATE_UINT64(env.vstimecmp, RISCVCPU),
VMSTATE_UINTTL(env.hvictl, RISCVCPU),
VMSTATE_UINT8_ARRAY(env.hviprio, RISCVCPU, 64),