diff options
| author | Frank Chang <frank.chang@sifive.com> | 2021-12-10 15:56:24 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-12-20 14:51:36 +1000 |
| commit | 5c4eb8fb5649f1fd137fb4d85a019332908fe066 (patch) | |
| tree | d5a826baaee5c822b0f38f98efbe976e8c301907 /target/riscv/internals.h | |
| parent | c4b3e46f0092ee9303787ae12ea9869eebcdc1ac (diff) | |
target/riscv: rvv-1.0: floating-point scalar move instructions
NaN-boxed the scalar floating-point register based on RVV 1.0's rules.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-39-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/internals.h')
| -rw-r--r-- | target/riscv/internals.h | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 81f5dfa477..ac062dc0b4 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -32,11 +32,6 @@ target_ulong fclass_h(uint64_t frs1); target_ulong fclass_s(uint64_t frs1); target_ulong fclass_d(uint64_t frs1); -#define SEW8 0 -#define SEW16 1 -#define SEW32 2 -#define SEW64 3 - #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_riscv_cpu; #endif |