diff options
| author | LIU Zhiwei <zhiwei_liu@c-sky.com> | 2020-07-01 23:24:54 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-07-02 09:19:32 -0700 |
| commit | 751538d5da557e5c10e5045c2d27639580ea54a7 (patch) | |
| tree | 200bf2ff45ca3ae14c0c6baadd220cf9a3835be3 /target/riscv/internals.h | |
| parent | f476f17740ad42288d42dd8fedcdae8ca7007a16 (diff) | |
target/riscv: add vector stride load and store instructions
Vector strided operations access the first memory element at the base address,
and then access subsequent elements at address increments given by the byte
offset contained in the x register specified by rs2.
Vector unit-stride operations access elements stored contiguously in memory
starting from the base effective address. It can been seen as a special
case of strided operations.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200701152549.1218-7-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/internals.h')
| -rw-r--r-- | target/riscv/internals.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 22a49af413..3253e73474 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -21,4 +21,9 @@ #include "hw/registerfields.h" +/* share data between vector helpers and decode code */ +FIELD(VDATA, MLEN, 0, 8) +FIELD(VDATA, VM, 8, 1) +FIELD(VDATA, LMUL, 9, 2) +FIELD(VDATA, NF, 11, 4) #endif |