diff options
| author | Mayuresh Chitale <mchitale@ventanamicro.com> | 2022-10-16 18:17:24 +0530 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-01-06 10:42:55 +1000 |
| commit | fb3f3730e405e2451dffc03c572037c2e0bd44c0 (patch) | |
| tree | 7a1b49daf2d8e8e409cb08f258ebccc911004e43 /target/riscv/insn_trans/trans_rvi.c.inc | |
| parent | 252b06f638cdc79aa6dc33e91174b276eb69b3e0 (diff) | |
target/riscv: generate virtual instruction exception
This patch adds a mechanism to generate a virtual instruction
instruction exception instead of an illegal instruction exception
during instruction decode when virt is enabled.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221016124726.102129-4-mchitale@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/insn_trans/trans_rvi.c.inc')
0 files changed, 0 insertions, 0 deletions