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| author | Travis Geiselbrecht <travisg@gmail.com> | 2021-10-08 22:50:19 -0700 |
|---|---|---|
| committer | Alistair Francis <alistair@alistair23.me> | 2021-10-22 07:47:51 +1000 |
| commit | e573a7f325e4d66d1005f7bb80d51ce95f307951 (patch) | |
| tree | 7652bc25f5ee55818fd2f74a49513bcb04f58459 /target/riscv/insn_trans/trans_rvb.c.inc | |
| parent | c672f19f328922eff4963b0b61fbdcfa661e1c06 (diff) | |
target/riscv: line up all of the registers in the info register dump
Ensure the columns for all of the register names and values line up.
No functional change, just a minor tweak to the output.
Signed-off-by: Travis Geiselbrecht <travisg@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211009055019.545153-1-travisg@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/insn_trans/trans_rvb.c.inc')
0 files changed, 0 insertions, 0 deletions