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authorRichard Henderson <richard.henderson@linaro.org>2021-10-19 20:17:02 -0700
committerAlistair Francis <alistair@alistair23.me>2021-10-22 07:47:51 +1000
commit905b9fcde1fb84d718d95369c5d886bc81bbdd8e (patch)
treeabeb2c09531c1c579550c8bee2ad647516d269fa /target/riscv/insn_trans/trans_rvb.c.inc
parent4e97d459a0f2b92815c2c2c6eb96b75e2235b42e (diff)
target/riscv: Replace is_32bit with get_xl/get_xlen
In preparation for RV128, replace a simple predicate with a more versatile test. Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20211020031709.359469-9-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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