diff options
| author | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2019-02-13 07:53:51 -0800 |
|---|---|---|
| committer | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2019-03-13 10:34:06 +0100 |
| commit | 6f0e74ff4b7f83901e99e59108eaa43513a0ce36 (patch) | |
| tree | cdfb736820e202c89a439bf2caf7ebb03894224f /target/riscv/insn32.decode | |
| parent | 40b9faecfe8000520958f50a77ea16f4b3dd6405 (diff) | |
target/riscv: Convert RV32F insns to decodetree
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
Diffstat (limited to 'target/riscv/insn32.decode')
| -rw-r--r-- | target/riscv/insn32.decode | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 00b9e2d9a5..e40836bf03 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -17,12 +17,14 @@ # this program. If not, see <http://www.gnu.org/licenses/>. # Fields: +%rs3 27:5 %rs2 20:5 %rs1 15:5 %rd 7:5 %sh10 20:10 %csr 20:12 +%rm 12:3 # immediates: %imm_i 20:s12 @@ -50,6 +52,11 @@ @atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd @atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2 %rs1 %rd +@r4_rm ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd +@r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd +@r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd +@r2 ....... ..... ..... ... ..... ....... %rs1 %rd + # *** RV32I Base Instruction Set *** lui .................... ..... 0110111 @u auipc .................... ..... 0010111 @u @@ -119,3 +126,31 @@ amomin_w 10000 . . ..... ..... 010 ..... 0101111 @atom_st amomax_w 10100 . . ..... ..... 010 ..... 0101111 @atom_st amominu_w 11000 . . ..... ..... 010 ..... 0101111 @atom_st amomaxu_w 11100 . . ..... ..... 010 ..... 0101111 @atom_st + +# *** RV32F Standard Extension *** +flw ............ ..... 010 ..... 0000111 @i +fsw ....... ..... ..... 010 ..... 0100111 @s +fmadd_s ..... 00 ..... ..... ... ..... 1000011 @r4_rm +fmsub_s ..... 00 ..... ..... ... ..... 1000111 @r4_rm +fnmsub_s ..... 00 ..... ..... ... ..... 1001011 @r4_rm +fnmadd_s ..... 00 ..... ..... ... ..... 1001111 @r4_rm +fadd_s 0000000 ..... ..... ... ..... 1010011 @r_rm +fsub_s 0000100 ..... ..... ... ..... 1010011 @r_rm +fmul_s 0001000 ..... ..... ... ..... 1010011 @r_rm +fdiv_s 0001100 ..... ..... ... ..... 1010011 @r_rm +fsqrt_s 0101100 00000 ..... ... ..... 1010011 @r2_rm +fsgnj_s 0010000 ..... ..... 000 ..... 1010011 @r +fsgnjn_s 0010000 ..... ..... 001 ..... 1010011 @r +fsgnjx_s 0010000 ..... ..... 010 ..... 1010011 @r +fmin_s 0010100 ..... ..... 000 ..... 1010011 @r +fmax_s 0010100 ..... ..... 001 ..... 1010011 @r +fcvt_w_s 1100000 00000 ..... ... ..... 1010011 @r2_rm +fcvt_wu_s 1100000 00001 ..... ... ..... 1010011 @r2_rm +fmv_x_w 1110000 00000 ..... 000 ..... 1010011 @r2 +feq_s 1010000 ..... ..... 010 ..... 1010011 @r +flt_s 1010000 ..... ..... 001 ..... 1010011 @r +fle_s 1010000 ..... ..... 000 ..... 1010011 @r +fclass_s 1110000 00000 ..... 001 ..... 1010011 @r2 +fcvt_s_w 1101000 00000 ..... ... ..... 1010011 @r2_rm +fcvt_s_wu 1101000 00001 ..... ... ..... 1010011 @r2_rm +fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2 |