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authorPhilipp Tomsich <philipp.tomsich@vrull.eu>2021-09-11 16:00:08 +0200
committerAlistair Francis <alistair.francis@wdc.com>2021-10-07 08:33:13 +1000
commitf36a4a89aad493990084a9b540ed511cb66701ce (patch)
tree160d1f80198aecf8b31deb6d024948a2c1fa5ff6 /target/riscv/insn32.decode
parent628d8c88c14e6ee8eef0c6d3b7178dbfc7770f03 (diff)
target/riscv: Reassign instructions to the Zbs-extension
The following instructions are part of Zbs: - b{set,clr,ext,inv} - b{set,clr,ext,inv}i Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210911140016.834071-9-philipp.tomsich@vrull.eu Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/insn32.decode')
-rw-r--r--target/riscv/insn32.decode17
1 files changed, 9 insertions, 8 deletions
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index e0f6e315a2..35a3563ff4 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -689,19 +689,11 @@ min 0000101 .......... 100 ..... 0110011 @r
minu 0000101 .......... 101 ..... 0110011 @r
max 0000101 .......... 110 ..... 0110011 @r
maxu 0000101 .......... 111 ..... 0110011 @r
-bset 0010100 .......... 001 ..... 0110011 @r
-bclr 0100100 .......... 001 ..... 0110011 @r
-binv 0110100 .......... 001 ..... 0110011 @r
-bext 0100100 .......... 101 ..... 0110011 @r
ror 0110000 .......... 101 ..... 0110011 @r
rol 0110000 .......... 001 ..... 0110011 @r
grev 0110100 .......... 101 ..... 0110011 @r
gorc 0010100 .......... 101 ..... 0110011 @r
-bseti 00101. ........... 001 ..... 0010011 @sh
-bclri 01001. ........... 001 ..... 0010011 @sh
-binvi 01101. ........... 001 ..... 0010011 @sh
-bexti 01001. ........... 101 ..... 0010011 @sh
rori 01100. ........... 101 ..... 0010011 @sh
grevi 01101. ........... 101 ..... 0010011 @sh
gorci 00101. ........... 101 ..... 0010011 @sh
@@ -722,3 +714,12 @@ roriw 0110000 .......... 101 ..... 0011011 @sh5
greviw 0110100 .......... 101 ..... 0011011 @sh5
gorciw 0010100 .......... 101 ..... 0011011 @sh5
+# *** RV32 Zbs Standard Extension ***
+bclr 0100100 .......... 001 ..... 0110011 @r
+bclri 01001. ........... 001 ..... 0010011 @sh
+bext 0100100 .......... 101 ..... 0110011 @r
+bexti 01001. ........... 101 ..... 0010011 @sh
+binv 0110100 .......... 001 ..... 0110011 @r
+binvi 01101. ........... 001 ..... 0010011 @sh
+bset 0010100 .......... 001 ..... 0110011 @r
+bseti 00101. ........... 001 ..... 0010011 @sh