diff options
| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-04-23 10:35:05 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-04-29 10:47:45 +1000 |
| commit | e9a7ef5d5e3f6595d03495d8fe8f72f4086ba3c4 (patch) | |
| tree | 6c6035c48481b19295112a6188f8338ddf0775e9 /target/riscv/insn32.decode | |
| parent | 387e5d92713b7d85f1d077466ac0a21d7f985858 (diff) | |
target/riscv: rvk: add support for sha512 related instructions for RV32 in zknh extension
- add sha512sum0r, sha512sig0l, sha512sum1r, sha512sig1l, sha512sig0h and sha512sig1h instructions
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220423023510.30794-10-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/insn32.decode')
| -rw-r--r-- | target/riscv/insn32.decode | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index db28ecdd2b..02a0c71890 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -862,3 +862,9 @@ sha256sig0 00 01000 00010 ..... 001 ..... 0010011 @r2 sha256sig1 00 01000 00011 ..... 001 ..... 0010011 @r2 sha256sum0 00 01000 00000 ..... 001 ..... 0010011 @r2 sha256sum1 00 01000 00001 ..... 001 ..... 0010011 @r2 +sha512sum0r 01 01000 ..... ..... 000 ..... 0110011 @r +sha512sum1r 01 01001 ..... ..... 000 ..... 0110011 @r +sha512sig0l 01 01010 ..... ..... 000 ..... 0110011 @r +sha512sig0h 01 01110 ..... ..... 000 ..... 0110011 @r +sha512sig1l 01 01011 ..... ..... 000 ..... 0110011 @r +sha512sig1h 01 01111 ..... ..... 000 ..... 0110011 @r |