diff options
| author | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2019-02-13 07:53:44 -0800 |
|---|---|---|
| committer | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2019-03-13 10:34:06 +0100 |
| commit | 7e45a682edc32ba90d6955215f062210531b835b (patch) | |
| tree | 1ebb0957508514c38733ca8df2fab7d1d7ce0ea9 /target/riscv/insn32-64.decode | |
| parent | c1000d4e1bdb13857b601c425aca2fda9131283b (diff) | |
target/riscv: Convert RV64I load/store insns to decodetree
this splits the 64-bit only instructions into its own decode file such
that we generate the decoder for these instructions only for the RISC-V
64 bit target.
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
Diffstat (limited to 'target/riscv/insn32-64.decode')
| -rw-r--r-- | target/riscv/insn32-64.decode | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode new file mode 100644 index 0000000000..439d4e2c58 --- /dev/null +++ b/target/riscv/insn32-64.decode @@ -0,0 +1,25 @@ +# +# RISC-V translation routines for the RV Instruction Set. +# +# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de +# Bastian Koppelmann, kbastian@mail.uni-paderborn.de +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2 or later, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. +# +# You should have received a copy of the GNU General Public License along with +# this program. If not, see <http://www.gnu.org/licenses/>. + +# This is concatenated with insn32.decode for risc64 targets. +# Most of the fields and formats are there. + +# *** RV64I Base Instruction Set (in addition to RV32I) *** +lwu ............ ..... 110 ..... 0000011 @i +ld ............ ..... 011 ..... 0000011 @i +sd ....... ..... ..... 011 ..... 0100011 @s |