diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2019-04-25 10:26:36 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-05-24 12:09:25 -0700 |
| commit | 4cc16b3b9282e04fab8e84d136540757e82af019 (patch) | |
| tree | a6caaae619e90e0d1bd36105f1fb986847435c53 /target/riscv/insn16-64.decode | |
| parent | e06431108b0b1ef6ca76398d2b0b792ea24ae6bc (diff) | |
target/riscv: Add checks for several RVC reserved operands
C.ADDI16SP, C.LWSP, C.JR, C.ADDIW, C.LDSP all have reserved
operands that were not diagnosed.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'target/riscv/insn16-64.decode')
| -rw-r--r-- | target/riscv/insn16-64.decode | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/target/riscv/insn16-64.decode b/target/riscv/insn16-64.decode index 055859d29f..672e1e916f 100644 --- a/target/riscv/insn16-64.decode +++ b/target/riscv/insn16-64.decode @@ -21,10 +21,16 @@ ld 011 ... ... .. ... 00 @cl_d sd 111 ... ... .. ... 00 @cs_d # *** RV64C Standard Extension (Quadrant 1) *** -addiw 001 . ..... ..... 01 @ci +{ + illegal 001 - 00000 ----- 01 # c.addiw, RES rd=0 + addiw 001 . ..... ..... 01 @ci +} subw 100 1 11 ... 00 ... 01 @cs_2 addw 100 1 11 ... 01 ... 01 @cs_2 # *** RV64C Standard Extension (Quadrant 2) *** -ld 011 . ..... ..... 10 @c_ldsp +{ + illegal 011 - 00000 ----- 10 # c.ldsp, RES rd=0 + ld 011 . ..... ..... 10 @c_ldsp +} sd 111 . ..... ..... 10 @c_sdsp |