diff options
| author | Rajnesh Kanwal <rkanwal@rivosinc.com> | 2023-10-16 12:17:36 +0100 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-11-07 11:02:17 +1000 |
| commit | 40336d5b1d4c6b8b8b38c77fda254457d44fe90b (patch) | |
| tree | 3dcea675926643687a22a84d0f174de6881425dd /target/riscv/gdbstub.c | |
| parent | 1697837ed98cf56a6f65edd06128151f83b99403 (diff) | |
target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.
This change adds support for inserting virtual interrupts from HS-mode
into VS-mode using hvien and hvip csrs. This also allows for IRQ filtering
from HS-mode.
Also, the spec doesn't mandate the interrupt to be actually supported
in hardware. Which allows HS-mode to assert virtual interrupts to VS-mode
that have no connection to any real interrupt events.
This is defined as part of the AIA specification [0], "6.3.2 Virtual
interrupts for VS level".
[0]: https://github.com/riscv/riscv-aia/releases/download/1.0/riscv-interrupts-1.0.pdf
Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20231016111736.28721-7-rkanwal@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/gdbstub.c')
0 files changed, 0 insertions, 0 deletions