diff options
| author | Alistair Francis <alistair.francis@wdc.com> | 2020-01-31 17:01:43 -0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmerdabbelt@google.com> | 2020-02-27 13:45:25 -0800 |
| commit | bd023ce33b85d73791b7bc78fd04a8115c60995e (patch) | |
| tree | 571dca1fab0b14d1c5abfa5c200ef46110e5ac8b /target/riscv/gdbstub.c | |
| parent | af1fa0039c799a350bcde07b3d8a71dfde07d11b (diff) | |
target/riscv: Add the Hypervisor CSRs to CPUState
Add the Hypervisor CSRs to CPUState and at the same time (to avoid
bisect issues) update the CSR macros for the v0.5 Hyp spec.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'target/riscv/gdbstub.c')
| -rw-r--r-- | target/riscv/gdbstub.c | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 1a72f7be9c..2f32750f2f 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -130,6 +130,8 @@ static int csr_register_map[] = { CSR_MCAUSE, CSR_MTVAL, CSR_MIP, + CSR_MTINST, + CSR_MTVAL2, CSR_PMPCFG0, CSR_PMPCFG1, CSR_PMPCFG2, @@ -252,12 +254,11 @@ static int csr_register_map[] = { CSR_HEDELEG, CSR_HIDELEG, CSR_HIE, - CSR_HTVEC, - CSR_HSCRATCH, - CSR_HEPC, - CSR_HCAUSE, - CSR_HBADADDR, + CSR_HCOUNTEREN, + CSR_HTVAL, CSR_HIP, + CSR_HTINST, + CSR_HGATP, CSR_MBASE, CSR_MBOUND, CSR_MIBASE, |