diff options
| author | Sergey Matyukevich <sergey.matyukevich@syntacore.com> | 2023-01-31 20:09:55 +0300 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-02-07 08:19:23 +1000 |
| commit | 26934f9a95264221ed8e6d603b8099508fbd2a5e (patch) | |
| tree | 5966712ae7b1754cc85e35162a94cd36186965b8 /target/riscv/debug.c | |
| parent | 606a2439babb7d676af32e15232e94159d67bbeb (diff) | |
target/riscv: set tval for triggered watchpoints
According to privileged spec, if [sm]tval is written with a nonzero
value when a breakpoint exception occurs, then [sm]tval will contain
the faulting virtual address. Set tval to hit address when breakpoint
exception is triggered by hardware watchpoint.
Signed-off-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230131170955.752743-1-geomatsi@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/debug.c')
| -rw-r--r-- | target/riscv/debug.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/target/riscv/debug.c b/target/riscv/debug.c index bf4840a6a3..b091293069 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -761,7 +761,6 @@ void riscv_cpu_debug_excp_handler(CPUState *cs) if (cs->watchpoint_hit) { if (cs->watchpoint_hit->flags & BP_CPU) { - cs->watchpoint_hit = NULL; do_trigger_action(env, DBG_ACTION_BP); } } else { |