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authorRichard Henderson <richard.henderson@linaro.org>2023-04-12 13:43:24 +0200
committerAlistair Francis <alistair.francis@wdc.com>2023-05-05 10:49:50 +1000
commit696bacde957bc5cdabc7710abc316ef56184d928 (patch)
tree10b31131c74234c9373c50b35b48fef305a1512f /target/riscv/csr.c
parent9de7b7b5c7ca8e81c6d62b7c5c5a4753fa597bcb (diff)
target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index
Incorporate the virt_enabled and MPV checks into the cpu_mmu_index function, so we don't have to keep doing it within tlb_fill and subroutines. This also elides a flush on changes to MPV. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230325105429.1142530-17-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-17-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/csr.c')
-rw-r--r--target/riscv/csr.c6
1 files changed, 1 insertions, 5 deletions
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 4a4d852bd1..865ee9efda 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1294,7 +1294,7 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
val = legalize_mpp(env, get_field(mstatus, MSTATUS_MPP), val);
/* flush tlb on mstatus fields that affect VM */
- if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPV)) {
+ if ((val ^ mstatus) & MSTATUS_MXR) {
tlb_flush(env_cpu(env));
}
mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
@@ -1342,10 +1342,6 @@ static RISCVException write_mstatush(CPURISCVState *env, int csrno,
uint64_t valh = (uint64_t)val << 32;
uint64_t mask = MSTATUS_MPV | MSTATUS_GVA;
- if ((valh ^ env->mstatus) & (MSTATUS_MPV)) {
- tlb_flush(env_cpu(env));
- }
-
env->mstatus = (env->mstatus & ~mask) | (valh & mask);
return RISCV_EXCP_NONE;