diff options
author | Richard Henderson <richard.henderson@linaro.org> | 2021-08-23 12:55:21 -0700 |
---|---|---|
committer | Alistair Francis <alistair.francis@wdc.com> | 2021-09-01 11:59:12 +1000 |
commit | 33979526cad412b72afd1989a22dcd218b2ce170 (patch) | |
tree | 6a806a15bc58da0f051ed0e65ad4ccb42e4ad447 /target/riscv/csr.c | |
parent | 6ecf39e2dd854ff7ea21c365165c1957061263bb (diff) |
target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operation
We distinguish write-only by passing ret_value as NULL.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210823195529.560295-17-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/csr.c')
-rw-r--r-- | target/riscv/csr.c | 23 |
1 files changed, 15 insertions, 8 deletions
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 6d7f2c2a95..16bd859121 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -937,9 +937,12 @@ static RISCVException rmw_vsip(CPURISCVState *env, int csrno, /* Shift the S bits to their VS bit location in mip */ int ret = rmw_mip(env, 0, ret_value, new_value << 1, (write_mask << 1) & vsip_writable_mask & env->hideleg); - *ret_value &= VS_MODE_INTERRUPTS; - /* Shift the VS bits to their S bit location in vsip */ - *ret_value >>= 1; + + if (ret_value) { + *ret_value &= VS_MODE_INTERRUPTS; + /* Shift the VS bits to their S bit location in vsip */ + *ret_value >>= 1; + } return ret; } @@ -956,7 +959,9 @@ static RISCVException rmw_sip(CPURISCVState *env, int csrno, write_mask & env->mideleg & sip_writable_mask); } - *ret_value &= env->mideleg; + if (ret_value) { + *ret_value &= env->mideleg; + } return ret; } @@ -1072,8 +1077,9 @@ static RISCVException rmw_hvip(CPURISCVState *env, int csrno, int ret = rmw_mip(env, 0, ret_value, new_value, write_mask & hvip_writable_mask); - *ret_value &= hvip_writable_mask; - + if (ret_value) { + *ret_value &= hvip_writable_mask; + } return ret; } @@ -1084,8 +1090,9 @@ static RISCVException rmw_hip(CPURISCVState *env, int csrno, int ret = rmw_mip(env, 0, ret_value, new_value, write_mask & hip_writable_mask); - *ret_value &= hip_writable_mask; - + if (ret_value) { + *ret_value &= hip_writable_mask; + } return ret; } |