diff options
| author | Alistair Francis <alistair.francis@wdc.com> | 2019-10-08 15:04:18 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@dabbelt.com> | 2019-11-14 09:53:28 -0800 |
| commit | 7ec5d3030b9293ab631dd653f64bc933b6c82e65 (patch) | |
| tree | d296987c0cce26292ad67b885672f9104c2f7b4b /target/riscv/csr.c | |
| parent | f480f6e8c5ca9a27c046e3a273a4693d2475bdc2 (diff) | |
target/riscv: Remove atomic accesses to MIP CSR
Instead of relying on atomics to access the MIP register let's update
our helper function to instead just lock the IO mutex thread before
writing. This follows the same concept as used in PPC for handling
interrupts
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Palmer Dabbelt <palmer@dabbelt.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
Diffstat (limited to 'target/riscv/csr.c')
| -rw-r--r-- | target/riscv/csr.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 974c9c20b5..da02f9f0b1 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -579,7 +579,7 @@ static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value, if (mask) { old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask)); } else { - old_mip = atomic_read(&env->mip); + old_mip = env->mip; } if (ret_value) { |