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| author | Michael Clark <mjc@sifive.com> | 2018-03-03 01:31:11 +1300 |
|---|---|---|
| committer | Michael Clark <mjc@sifive.com> | 2018-03-07 08:30:28 +1300 |
| commit | 65c5b75c38b3e56650fc63674039108697096f75 (patch) | |
| tree | efc7daab35de8ad572ee08cca112c454f346e025 /target/riscv/cpu_user.h | |
| parent | 55c2a12cbcd3d417de39ee82dfe1d26b22a07116 (diff) | |
RISC-V Physical Memory Protection
Implements the physical memory protection extension as specified in
Privileged ISA Version 1.10.
PMP (Physical Memory Protection) is as-of-yet unused and needs testing.
The SiFive verification team have PMP test cases that will be run.
Nothing currently depends on PMP support. It would be preferable to keep
the code in-tree for folk that are interested in RISC-V PMP support.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Daire McNamara <daire.mcnamara@emdalo.com>
Signed-off-by: Ivan Griffin <ivan.griffin@emdalo.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Diffstat (limited to 'target/riscv/cpu_user.h')
0 files changed, 0 insertions, 0 deletions