diff options
author | Michael Clark <mjc@sifive.com> | 2019-03-16 01:21:21 +0000 |
---|---|---|
committer | Palmer Dabbelt <palmer@sifive.com> | 2019-03-19 05:14:40 -0700 |
commit | d9360e96885dbd69ce4aa925d1701c7a10cf54ae (patch) | |
tree | 54d472299af1d3e8d2de9783ff53e48772590c5f /target/riscv/cpu_helper.c | |
parent | 929f0a7fc40d7123ddda4c9dbd78a1806999b4f7 (diff) |
RISC-V: Update load reservation comment in do_interrupt
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'target/riscv/cpu_helper.c')
-rw-r--r-- | target/riscv/cpu_helper.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 6d3fbc3401..b17f169681 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -525,7 +525,13 @@ void riscv_cpu_do_interrupt(CPUState *cs) ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0); riscv_cpu_set_mode(env, PRV_M); } - /* TODO yield load reservation */ + + /* NOTE: it is not necessary to yield load reservations here. It is only + * necessary for an SC from "another hart" to cause a load reservation + * to be yielded. Refer to the memory consistency model section of the + * RISC-V ISA Specification. + */ + #endif cs->exception_index = EXCP_NONE; /* mark handled to qemu */ } |