diff options
author | Alistair Francis <alistair.francis@wdc.com> | 2021-04-01 11:17:29 -0400 |
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committer | Alistair Francis <alistair.francis@wdc.com> | 2021-05-11 20:02:06 +1000 |
commit | 330d2ae32af9a278bc8aa88d598f7750ff27f3dd (patch) | |
tree | ba139a94e8a4b885d7178630b8f6a64f044b1c81 /target/riscv/cpu_helper.c | |
parent | 8a2aca3d79f8719b9cf79fdcdfbb89bc6bdb522a (diff) |
target/riscv: Convert the RISC-V exceptions to an enum
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: f191dcf08bf413a822e743a7c7f824d68879a527.1617290165.git.alistair.francis@wdc.com
Diffstat (limited to 'target/riscv/cpu_helper.c')
-rw-r--r-- | target/riscv/cpu_helper.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 503c2559f8..99cc388db9 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -72,7 +72,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env) if (irqs) { return ctz64(irqs); /* since non-zero */ } else { - return EXCP_NONE; /* indicates no pending interrupt */ + return RISCV_EXCP_NONE; /* indicates no pending interrupt */ } } #endif @@ -1069,5 +1069,5 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->two_stage_lookup = false; #endif - cs->exception_index = EXCP_NONE; /* mark handled to qemu */ + cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */ } |