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authorAlistair Francis <alistair.francis@wdc.com>2020-03-27 12:53:40 -0700
committerAlistair Francis <alistair.francis@wdc.com>2020-06-19 08:24:07 -0700
commitefe9f9c820d1322729957a60ff785c9527a79ddf (patch)
tree3fb60b5f4c86bc1f6ee5bbe9ef8d8e0ea941ee5e /target/riscv/cpu_helper.c
parent2fdd2c094a3df68084df07de99ac5f7316c54145 (diff)
target/riscv: Set access as data_load when validating stage-2 PTEs
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/riscv/cpu_helper.c')
-rw-r--r--target/riscv/cpu_helper.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 62fe1ecc8f..eda7057663 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -435,7 +435,7 @@ restart:
hwaddr vbase;
/* Do the second stage translation on the base PTE address. */
- get_physical_address(env, &vbase, &vbase_prot, base, access_type,
+ get_physical_address(env, &vbase, &vbase_prot, base, MMU_DATA_LOAD,
mmu_idx, false, true);
pte_addr = vbase + idx * ptesize;