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authorMax Chou <max.chou@sifive.com>2023-10-26 23:18:15 +0800
committerAlistair Francis <alistair.francis@wdc.com>2023-11-07 11:06:02 +1000
commit8f913d1004766c8ee96bcab78a6c39764aa5ee52 (patch)
tree5472a13873a4b5d9a7d9f9295769759c9cf62b31 /target/riscv/cpu_cfg.h
parent23aaefb9c9900c385c74b3490e60da2040f8200e (diff)
target/riscv: Add cfg properties for Zvks[c|g] extensions
Vector crypto spec defines the ShangMi algorithm suite related extensions (Zvks, Zvksc, Zvksg) combined by several vector crypto extensions. Signed-off-by: Max Chou <max.chou@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20231026151828.754279-9-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu_cfg.h')
-rw-r--r--target/riscv/cpu_cfg.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index 08733002a7..634ff673b3 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -101,6 +101,9 @@ struct RISCVCPUConfig {
bool ext_zvkn;
bool ext_zvknc;
bool ext_zvkng;
+ bool ext_zvks;
+ bool ext_zvksc;
+ bool ext_zvksg;
bool ext_zmmul;
bool ext_zvfbfmin;
bool ext_zvfbfwma;