diff options
| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-08-16 22:19:16 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-09-11 11:45:55 +1000 |
| commit | ed67d63798f2ff31a7541ed97ac671c8e1f79297 (patch) | |
| tree | 937d75571131c03d4a0dd6a5bac720a9f29fd429 /target/riscv/cpu_bits.h | |
| parent | 9ff31406312500053ecb5f92df01dd9ce52e635d (diff) | |
target/riscv: Update CSR bits name for svadu extension
The Svadu specification updated the name of the *envcfg bit from
HADE to ADUE.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230816141916.66898-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu_bits.h')
| -rw-r--r-- | target/riscv/cpu_bits.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 31a8d80990..3d6ffaabc7 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -745,12 +745,12 @@ typedef enum RISCVException { #define MENVCFG_CBIE (3UL << 4) #define MENVCFG_CBCFE BIT(6) #define MENVCFG_CBZE BIT(7) -#define MENVCFG_HADE (1ULL << 61) +#define MENVCFG_ADUE (1ULL << 61) #define MENVCFG_PBMTE (1ULL << 62) #define MENVCFG_STCE (1ULL << 63) /* For RV32 */ -#define MENVCFGH_HADE BIT(29) +#define MENVCFGH_ADUE BIT(29) #define MENVCFGH_PBMTE BIT(30) #define MENVCFGH_STCE BIT(31) @@ -763,12 +763,12 @@ typedef enum RISCVException { #define HENVCFG_CBIE MENVCFG_CBIE #define HENVCFG_CBCFE MENVCFG_CBCFE #define HENVCFG_CBZE MENVCFG_CBZE -#define HENVCFG_HADE MENVCFG_HADE +#define HENVCFG_ADUE MENVCFG_ADUE #define HENVCFG_PBMTE MENVCFG_PBMTE #define HENVCFG_STCE MENVCFG_STCE /* For RV32 */ -#define HENVCFGH_HADE MENVCFGH_HADE +#define HENVCFGH_ADUE MENVCFGH_ADUE #define HENVCFGH_PBMTE MENVCFGH_PBMTE #define HENVCFGH_STCE MENVCFGH_STCE |