diff options
| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-04-07 09:47:42 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-05-05 10:49:50 +1000 |
| commit | 44b8f74b0088df22f30e0718f6aefa9fb87702f6 (patch) | |
| tree | 10f29752d34a2c3f63ff349dec28707324b00185 /target/riscv/cpu_bits.h | |
| parent | 04803c3ddb37a8c84392452c3596bd1c4474904d (diff) | |
target/riscv: Use PRV_RESERVED instead of PRV_H
PRV_H has no real meaning, but just a reserved privilege mode currently.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230407014743.18779-3-liweiwei@iscas.ac.cn>
[ Changes by AF:
- Convert one missing use of PRV_H
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu_bits.h')
| -rw-r--r-- | target/riscv/cpu_bits.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 101702cb4a..a16bfaf43f 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -608,7 +608,7 @@ typedef enum { /* Privilege modes */ #define PRV_U 0 #define PRV_S 1 -#define PRV_H 2 /* Reserved */ +#define PRV_RESERVED 2 #define PRV_M 3 /* RV32 satp CSR field masks */ |