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| author | Michael Tokarev <mjt@tls.msk.ru> | 2023-07-14 14:19:10 +0300 |
|---|---|---|
| committer | Michael Tokarev <mjt@tls.msk.ru> | 2023-09-08 13:08:52 +0300 |
| commit | 42fe74998cb8100fa7bb6afcafd2bd329749dc8f (patch) | |
| tree | 30244f44f2158f9a0cb10e9121a17fd72f33e962 /target/riscv/cpu_bits.h | |
| parent | 6c67d98c4afb0a2f170b52b77e5a8c7841f9e7a1 (diff) | |
riscv: spelling fixes
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu_bits.h')
| -rw-r--r-- | target/riscv/cpu_bits.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 59f0ffd9e1..31a8d80990 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -656,7 +656,7 @@ typedef enum { /* Leaf page shift amount */ #define PGSHIFT 12 -/* Default Reset Vector adress */ +/* Default Reset Vector address */ #define DEFAULT_RSTVEC 0x1000 /* Exception causes */ @@ -740,7 +740,7 @@ typedef enum RISCVException { #define PM_CURRENT 0x00000002ULL #define PM_INSN 0x00000004ULL -/* Execution enviornment configuration bits */ +/* Execution environment configuration bits */ #define MENVCFG_FIOM BIT(0) #define MENVCFG_CBIE (3UL << 4) #define MENVCFG_CBCFE BIT(6) |