diff options
| author | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2021-09-11 16:00:15 +0200 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-10-07 08:41:33 +1000 |
| commit | 9916ea3c97f6cbd46d912ecc80dfe94baed5d288 (patch) | |
| tree | 31a71b2c8a333c48d20f4f7c55de8784363dc6b0 /target/riscv/cpu.h | |
| parent | 06dfa8a5c5e79c2be7672b0a56e08c7f6d350148 (diff) | |
target/riscv: Remove RVB (replaced by Zb[abcs])
With everything classified as Zb[abcs] and pre-0.93 draft-B
instructions that are not part of Zb[abcs] removed, we can remove the
remaining support code for RVB.
Note that RVB has been retired for good and misa.B will neither mean
'some' or 'all of' Zb*:
https://lists.riscv.org/g/tech-bitmanip/message/532
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210911140016.834071-16-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu.h')
| -rw-r--r-- | target/riscv/cpu.h | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 1a38723f2c..bd519c9090 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -67,7 +67,6 @@ #define RVS RV('S') #define RVU RV('U') #define RVH RV('H') -#define RVB RV('B') /* S extension denotes that Supervisor mode exists, however it is possible to have a core that support S mode but does not have an MMU and there @@ -83,7 +82,6 @@ enum { #define PRIV_VERSION_1_10_0 0x00011000 #define PRIV_VERSION_1_11_0 0x00011100 -#define BEXT_VERSION_0_93_0 0x00009300 #define VEXT_VERSION_0_07_1 0x00000701 enum { @@ -288,7 +286,6 @@ struct RISCVCPU { bool ext_f; bool ext_d; bool ext_c; - bool ext_b; bool ext_s; bool ext_u; bool ext_h; |