diff options
| author | Atish Patra <atishp@rivosinc.com> | 2022-03-03 10:54:39 -0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-04-22 10:35:16 +1000 |
| commit | 29a9ec9bd8a7a7a4d98aa9a2260db6b2e815fb77 (patch) | |
| tree | 607eadf2628526052f15eb202a9528f927a8c0dc /target/riscv/cpu.h | |
| parent | 3e6a417c8a077595ebcb4fb1d0944b291564cd43 (diff) | |
target/riscv: Add *envcfg* CSRs support
The RISC-V privileged specification v1.12 defines few execution
environment configuration CSRs that can be used enable/disable
extensions per privilege levels.
Add the basic support for these CSRs.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220303185440.512391-6-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu.h')
| -rw-r--r-- | target/riscv/cpu.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5139110c4f..e129c3da7d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -304,6 +304,11 @@ struct CPUArchState { target_ulong spmbase; target_ulong upmmask; target_ulong upmbase; + + /* CSRs for execution enviornment configuration */ + uint64_t menvcfg; + target_ulong senvcfg; + uint64_t henvcfg; #endif target_ulong cur_pmmask; target_ulong cur_pmbase; |