diff options
| author | Yifei Jiang <jiangyifei@huawei.com> | 2022-01-12 16:13:26 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-01-21 15:52:56 +1000 |
| commit | 27abe66f31efa8bcd15f0f998db2127b4ffb628a (patch) | |
| tree | ce03dd7ec2f27e92cb2d23cd88c87239de639422 /target/riscv/cpu.h | |
| parent | 10f1ca27e0fe9930d372591cd5f302e7249aa705 (diff) | |
target/riscv: Add kvm_riscv_get/put_regs_timer
Add kvm_riscv_get/put_regs_timer to synchronize virtual time context
from KVM.
To set register of RISCV_TIMER_REG(state) will occur a error from KVM
on kvm_timer_state == 0. It's better to adapt in KVM, but it doesn't matter
that adaping in QEMU.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220112081329.1835-11-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu.h')
| -rw-r--r-- | target/riscv/cpu.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 73ced2116b..22c94d3c57 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -273,6 +273,13 @@ struct CPURISCVState { hwaddr kernel_addr; hwaddr fdt_addr; + + /* kvm timer */ + bool kvm_timer_dirty; + uint64_t kvm_timer_time; + uint64_t kvm_timer_compare; + uint64_t kvm_timer_state; + uint64_t kvm_timer_frequency; }; OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass, |