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authorDaniel Henrique Barboza <dbarboza@ventanamicro.com>2023-12-18 09:53:28 -0300
committerAlistair Francis <alistair.francis@wdc.com>2024-01-10 18:47:47 +1000
commit1a7d4fcb3fe9d4215b3d6ead362af379a82c1c49 (patch)
tree553c8390759fb0c16425fb34b6c18f2d991584c6 /target/riscv/cpu.h
parent48531f5adb2aede5519d072b9bbc27f46994ce2d (diff)
target/riscv: add priv ver restriction to profiles
Some profiles, like RVA22S64, has a priv_spec requirement. Make this requirement explicit for all profiles. We'll validate this requirement finalize() time and, in case the user chooses an incompatible priv_spec while activating a profile, a warning will be shown. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20231218125334.37184-21-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu.h')
-rw-r--r--target/riscv/cpu.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 5af1666dc0..3d1c347b71 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -81,10 +81,12 @@ typedef struct riscv_cpu_profile {
uint32_t misa_ext;
bool enabled;
bool user_set;
+ int priv_spec;
const int32_t ext_offsets[];
} RISCVCPUProfile;
#define RISCV_PROFILE_EXT_LIST_END -1
+#define RISCV_PROFILE_ATTR_UNUSED -1
extern RISCVCPUProfile *riscv_profiles[];