diff options
| author | LIU Zhiwei <zhiwei_liu@linux.alibaba.com> | 2023-04-12 13:43:09 +0200 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-05-05 10:49:50 +1000 |
| commit | f196639024fb460b7f5bbee39215b90b58810788 (patch) | |
| tree | 955f50a8b04a3b9924aeb086992162776377b439 /target/riscv/cpu.h | |
| parent | d6db7c975e2e0d60850043ea8f208dd446a61d0a (diff) | |
target/riscv: Extract virt enabled state from tb flags
Virt enabled state is not a constant, so we should put it into tb flags.
Thus we can use it like a constant condition at translation phase.
Reported-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230324143031.1093-2-zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-2-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-2-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu.h')
| -rw-r--r-- | target/riscv/cpu.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 86e08d10da..aa53d0e256 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -648,6 +648,8 @@ FIELD(TB_FLAGS, VTA, 24, 1) FIELD(TB_FLAGS, VMA, 25, 1) /* Native debug itrigger */ FIELD(TB_FLAGS, ITRIGGER, 26, 1) +/* Virtual mode enabled */ +FIELD(TB_FLAGS, VIRT_ENABLED, 27, 1) #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) |