diff options
| author | Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> | 2022-01-06 22:00:57 +0100 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-01-08 15:46:10 +1000 |
| commit | 332dab68785bba0381790fef94f4f433e8e806ea (patch) | |
| tree | c0e0521748bb4eb4eeba05e71ac458e4038ef977 /target/riscv/cpu.h | |
| parent | 2b5470843a6bf10bcc4431d81badec6bfe31f0a7 (diff) | |
target/riscv: setup everything for rv64 to support rv128 execution
This patch adds the support of the '-cpu rv128' option to
qemu-system-riscv64 so that we can indicate that we want to run rv128
executables.
Still, there is no support for 128-bit insns at that stage so qemu fails
miserably (as expected) if launched with this option.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-8-frederic.petrot@univ-grenoble-alpes.fr
[ Changed by AF
- Rename CPU to "x-rv128"
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu.h')
| -rw-r--r-- | target/riscv/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index fa5d238530..fd583e0f41 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -38,6 +38,7 @@ #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") +#define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") |