diff options
| author | Alistair Francis <alistair.francis@wdc.com> | 2020-01-31 17:02:56 -0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmerdabbelt@google.com> | 2020-02-27 13:46:29 -0800 |
| commit | 36a18664bafcfafa5e997b47458387f6fe53d537 (patch) | |
| tree | 993c99a81afa634990b6bf8e515143dbf032b7a1 /target/riscv/cpu.h | |
| parent | 1448689c7b23690f49a4cce248c6e4ac973d37b8 (diff) | |
target/riscv: Implement second stage MMU
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'target/riscv/cpu.h')
| -rw-r--r-- | target/riscv/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index aa04e5cca7..a8534fdf2b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -104,6 +104,7 @@ struct CPURISCVState { target_ulong frm; target_ulong badaddr; + target_ulong guest_phys_fault_addr; target_ulong priv_ver; target_ulong misa; |