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authorAlistair Francis <alistair.francis@wdc.com>2020-01-31 17:03:11 -0800
committerPalmer Dabbelt <palmerdabbelt@google.com>2020-02-27 13:46:34 -0800
commitc9eefe05a42d05d7a6dc49805f123579e5558d5d (patch)
tree37279fedf0b69d925880b6eca4dfb7b3abe2c35d /target/riscv/cpu.h
parente44b50b5b2e508fdd24915ab0e44ac49685e1de3 (diff)
target/riscv: Allow enabling the Hypervisor extension
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'target/riscv/cpu.h')
-rw-r--r--target/riscv/cpu.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 6f9c29322a..d52f209361 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -258,6 +258,7 @@ typedef struct RISCVCPU {
bool ext_c;
bool ext_s;
bool ext_u;
+ bool ext_h;
bool ext_counters;
bool ext_ifencei;
bool ext_icsr;