diff options
| author | Alistair Francis <alistair.francis@wdc.com> | 2021-04-01 11:18:07 -0400 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-05-11 20:02:06 +1000 |
| commit | 533c91e8f22cf86bb7b87f12c13024291d7d66fc (patch) | |
| tree | c8c8f51582cb2f0e9794beec2bcff4c47e9bd014 /target/riscv/cpu.h | |
| parent | 605def6eeee5e4b6293963aa86be6e637e48bfb3 (diff) | |
target/riscv: Use RISCVException enum for CSR access
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 302b208f40373557fa11b351b5c9f43039ca8ea3.1617290165.git.alistair.francis@wdc.com
Diffstat (limited to 'target/riscv/cpu.h')
| -rw-r--r-- | target/riscv/cpu.h | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a7b8876ea0..842d3ab810 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -454,10 +454,13 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, *pflags = flags; } -int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, - target_ulong new_value, target_ulong write_mask); -int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value, - target_ulong new_value, target_ulong write_mask); +RISCVException riscv_csrrw(CPURISCVState *env, int csrno, + target_ulong *ret_value, + target_ulong new_value, target_ulong write_mask); +RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, + target_ulong *ret_value, + target_ulong new_value, + target_ulong write_mask); static inline void riscv_csr_write(CPURISCVState *env, int csrno, target_ulong val) |