diff options
| author | Jim Wilson <jimw@sifive.com> | 2019-03-15 03:26:58 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-03-19 05:13:24 -0700 |
| commit | 753e3fe207db08ce0ef0405e8452c3397c9b9308 (patch) | |
| tree | 38d16fb6f1b727dafe750f2e4f638d50f0803132 /target/riscv/cpu.h | |
| parent | 8e73df6aa3f2f0e5c26c03a94a88406616291815 (diff) | |
RISC-V: Add debug support for accessing CSRs.
Add a debugger field to CPURISCVState. Add riscv_csrrw_debug function
to set it. Disable mode checks when debugger field true.
Signed-off-by: Jim Wilson <jimw@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20190212230903.9215-1-jimw@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'target/riscv/cpu.h')
| -rw-r--r-- | target/riscv/cpu.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5c2aebf132..4c5de30b37 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -172,6 +172,9 @@ struct CPURISCVState { /* physical memory protection */ pmp_table_t pmp_state; + + /* True if in debugger mode. */ + bool debugger; #endif float_status fp_status; @@ -293,6 +296,8 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, target_ulong new_value, target_ulong write_mask); +int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value, + target_ulong new_value, target_ulong write_mask); static inline void riscv_csr_write(CPURISCVState *env, int csrno, target_ulong val) |